Semiconductor memory devices

ABSTRACT

A semiconductor memory device may include: a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on a substrate; a lower semiconductor pattern that protrudes from the top of the substrate; a vertical insulating pattern that extends in a vertical direction from the substrate and penetrates the stacking structure; and a vertical channel pattern on the inner surface of the vertical insulating pattern and contacting the lower semiconductor pattern, wherein an upper part of the lower semiconductor pattern includes a recess region including a curve-shaped profile, and in the recess region, the outer surface of a lower part of the vertical channel pattern contacts the lower semiconductor pattern along a curve of the recess region.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.15/480,983, filed on Apr. 6, 2017, which claims priority under 35 U.S.C.§ 119 to Korean Patent Application No. 10-2016-0128216 filed in theKorean Intellectual Property Office on Oct. 5, 2016, the entire contentsof which are incorporated herein by reference.

BACKGROUND (a) Field

The present inventive concepts relate to semiconductor memory devices.

(b) Description of the Related Art

The price and performance demands of consumers have created anincreasing need for semiconductor memory devices with improvedintegrity. In the case of 2D or planar semiconductor memory devices,since the integrity can be determined, in part, by an area occupied by aunit memory cell, the integrity may be influenced by a level of a micropattern forming technology. However, since the equipment used formicronization of a pattern can be expensive, the integrity of the 2Dsemiconductor memory devices may be limited.

SUMMARY

The present inventive concepts provide semiconductor memory deviceshaving improved reliability.

The present inventive concepts are not limited to the aforementionedtechnical object, and other technical objects, which are not mentionedabove, will be appreciated by a person having ordinary skill in the artfrom the following description.

An example embodiment of the present inventive concepts provides asemiconductor memory device including: a stacking structure including aplurality of insulating layers and a plurality of gate electrodesalternately stacked on a substrate; a lower semiconductor pattern thatprotrudes from the substrate; a vertical insulating pattern that extendsin a vertical direction from the substrate and penetrates the stackingstructure; and a vertical channel pattern on an inner surface of thevertical insulating pattern and contacting the lower semiconductorpattern, wherein an upper part of the lower semiconductor patternincludes a recess region including a curve-shaped profile, and in therecess region, an outer surface of a lower part of the vertical channelpattern contacts the lower semiconductor pattern along a curve of therecess region.

Another example embodiment of the present inventive concepts provides asemiconductor memory device including: a stacking structure including aplurality of insulating layers and a plurality of gate electrodesalternately stacked on a substrate; a lower semiconductor pattern thatprotrudes from the substrate; a vertical insulating pattern whichextends in a vertical direction to the substrate and penetrates thestacking structure; and a vertical channel pattern positioned on aninner surface of the vertical insulating pattern and contacting thelower semiconductor pattern, wherein the lower semiconductor patternincludes a first region doped with a first impurity, and a second regiondoped with a second impurity having the same conductive type as thesubstrate.

Another example embodiment of the present inventive concepts provides asemiconductor memory device including a substrate, a stacking structurecomprising a plurality of insulating layers and a plurality of gateelectrodes alternately stacked on the substrate, a lower semiconductorpattern extending in a first direction from the substrate, a verticalchannel pattern on the lower semiconductor pattern and extending in thefirst direction from within a recess region of the lower semiconductorpattern, and a vertical insulating pattern extending in the firstdirection between the vertical channel pattern and the stackingstructure. A first region of the lower semiconductor pattern may includea first impurity. A second region of the lower semiconductor patternbetween the first region and the substrate may include a second impuritydifferent from the first impurity.

According to example embodiments of the present inventive concepts,since semiconductor memory devices may include a vertical channelpattern having a small thickness, electron mobility of a channel canincrease and electrical characteristics of the semiconductor memorydevices can be improved.

Further, a lower semiconductor pattern may be inhibited or preventedfrom being excessively etched during a manufacturing process to reduceor prevent disconnection of the vertical channel pattern having thesmall thickness, which contacts the lower semiconductor pattern. As aresult, semiconductor memory devices having improved reliability can beprovided.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and other advantages of thepresent inventive concepts will be more clearly understood from thefollowing detailed description when taken in conjunction with theaccompanying drawings, in which:

FIG. 1 is a schematic circuit diagram illustrating a 3D semiconductormemory cell array according to an example embodiment of the presentinventive concepts.

FIG. 2A is a perspective view illustrating a part of a semiconductormemory device according to an example embodiment of the presentinventive concepts, FIG. 2B is an enlarged diagram of region A of FIG.2A, and FIG. 2C is a cross-sectional view taken along line C-C of FIG.2B.

FIG. 3A is a perspective view illustrating a part of a semiconductormemory device according to another example embodiment of the presentinventive concepts and FIG. 3B is an enlarged diagram of region A ofFIG. 3A.

FIG. 4A is a perspective view illustrating a part of a semiconductormemory device according to another example embodiment of the presentinventive concepts and FIG. 4B is an enlarged diagram of region A ofFIG. 4A.

FIGS. 5, 6, 7, 8, 9A, 10A, 11A, 12A, 13A, 14A, 15, 16, 17, 18, 19, and20 are cross-sectional views for describing methods for manufacturingsemiconductor memory devices according to example embodiments of thepresent inventive concepts and FIGS. 9B, 10B, 11B, 12B, 13B, and 14B areenlarged diagrams of region A of the corresponding figures according tothe manufacturing methods.

FIGS. 21A and 21B are a cross-sectional view and an enlarged diagram,respectively, for describing methods for manufacturing semiconductormemory devices according to example embodiments of the present inventiveconcepts.

FIG. 22 is a diagram illustrating a cross-sectional shape of a lowersemiconductor pattern according to an example embodiment of the presentinventive concepts, and FIG. 23 is a diagram illustrating across-sectional shape of a lower semiconductor pattern according to acomparative example.

FIG. 24 is a graph illustrating current depending on gate voltageapplied to the example embodiment of FIG. 22 and the comparative exampleof FIG. 23, and FIG. 25 is a graph illustrating a worst on-cell currentcharacteristic.

FIG. 26 is a block diagram schematically illustrating one example of anelectronic system including a semiconductor memory device according toexample embodiments of the present inventive concepts, and FIG. 27 is ablock diagram schematically illustrating one example of a memory cardincluding a semiconductor memory device according to example embodimentsof the present inventive concepts.

DETAILED DESCRIPTION

FIG. 1 is a schematic circuit diagram illustrating a 3D semiconductormemory cell array according to an example embodiment of the presentinventive concepts.

Referring to FIG. 1, the memory cell array may include a plurality ofcell strings CS11, CS12, CS21, and CS22 which extend in a verticaldirection. The plurality of cell strings may have a vertical structurein which the plurality of cell strings extend in a perpendiculardirection (e.g., a z direction) to a plane of a substrate upon which theplurality of cell strings are formed.

The plurality of cell strings CS11, CS12, CS21, and CS22 may include aground selection transistor GST, a plurality of memory cell transistorsMC1, MC2, . . . , MC6, and a string selection transistor SST which areconnected in series, respectively. In FIG. 1, it is illustrated thateach of the cell strings CS11, CS12, CS21, and CS22 has one stringselection transistor SST, but the present inventive concepts are notlimited thereto. Further, it is illustrated that each of the cellstrings CS11, CS12, CS21, and CS22 has 6 memory cell transistors MC1,MC2, . . . , MC6, but each of the cell strings CS11, CS12, CS21, andCS22 may include at least 8 memory cell transistors MCx and the presentinventive concepts are not limited thereto.

The plurality of cell strings CS11, CS12, CS21, and CS22 may beconnected while being arranged in a matrix. The string selectiontransistor SST of each of the cell strings CS11, CS12, CS21, and CS22may be connected with corresponding bit lines BTL1 and BTL2. Forexample, the cell strings CS11 and CS21 commonly connected to the firstbit line BTL1 may be arrayed along a first column, and the cell stringsCS12 and CS22 commonly connected to the second bit line BTL2 may bearrayed along a second column. The string selection transistor SST ofeach of the cell strings CS11, CS12, CS21, and CS22 may be connectedwith string selection lines SSL1 and SSL2. For example, the cell stringsCS11 and CS12 commonly connected to the first string selection line SSL1may be arrayed along a first row, and the cell strings CS21 and CS22commonly connected to the second string selection line SSL2 may bearrayed along a second row.

The ground selection transistor GST of each of the cell strings CS11,CS12, CS21, and CS22 may be connected with the ground selection lineGSL. A common source line CSL may be connected with the ground selectiontransistor GST of each of the cell strings CS11, CS12, CS21, and CS22.

Memory cell transistors MC1, MC2, . . . , MC6 positioned at the sameheight may be connected to word lines WL1, WL2, . . . , WL6 positionedat the same height, respectively. For example, the first memory celltransistor MC1 connected with the ground selection transistor GST may beconnected with the first memory cell transistor MC1 of an adjacentcolumn through the first word line WL1.

The common source line CSL may be commonly connected to a source of theground selection transistor GST. In addition, the ground selection lineGSL, the plurality of word lines WL1, WL2, . . . , WL6, and the stringselection lines SSL1 and SSL2 disposed between the common source lineCSL and the bit lines BTL1 and BTL2 may be used as gate electrodes ofthe ground selection transistor GST, the memory cell transistors MC1,MC2, . . . , MC6, and the string selection transistor SST, respectively.Further, each of the memory cell transistors MC1, MC2, . . . , MC6 mayinclude a data storage element.

Hereinafter, a semiconductor memory device according to an exampleembodiment of the present inventive concepts will be described withreference to FIGS. 2A and 2B. FIG. 2A is a perspective view illustratinga part of a semiconductor memory device according to an exampleembodiment of the present inventive concepts, FIG. 2B is an enlargeddiagram of region A of FIG. 2A, and FIG. 2C is a cross-sectional viewtaken along line C-C of FIG. 2B.

Referring to FIGS. 2A and 2B, the semiconductor memory device accordingto the example embodiment may include a substrate 100 containing asemiconductor material. The substrate 100 may be, for example, a siliconsubstrate, a germanium substrate, a silicon-germanium substrate, or asilicon-on-insulator (SOI) substrate. The substrate 100 may include animpurity such as, for example, a P type impurity.

The substrate 100 may include a common source region 280 doped with theimpurity. The common source region 280 may extend in an x directionparallel to the top of the substrate 100. A plurality of common sourceregions 280 may be arranged in a y direction orthogonal to the xdirection. The common source region 280 may include, for example, an Ntype impurity injected in the substrate 100.

A stacking structure SS in which a plurality of insulating layers 110and a plurality of gate electrodes 300 are alternately stacked ispositioned on the substrate 100. A plurality of stacking structures SSmay be provided, but hereinafter, one stacking structure SS will beprimarily described.

With respect to an xy-direction plane, the stacking structure SS mayextend in the x direction and the common source regions 280 may bepositioned at both sides of the stacking structure SS. The stackingstructure SS and the common source region 280 may be alternatelypositioned in the y direction.

The common source line CSL may be positioned between adjacent stackingstructures SS and may penetrate the plurality of gate electrodes 300 andthe plurality of insulating layers 110 in a direction (e.g., a zdirection) perpendicular to the top of the substrate 100.

The common source line CSL may contact the substrate 100 and, in detail,contact the common source region 280 included in the substrate 100. Atrench spacer 285 disposed between the common source line CSL and thegate electrode 300 may electrically insulate the common source line CSLand the gate electrode 300 adjacent to each other in the y direction. Alower insulating layer 105 may be positioned between the substrate 100and the stacking structure SS. The lower insulating layer 105 mayinclude a high dielectric layer such as a silicon nitride layer, analuminum oxide layer, and/or a hafnium oxide layer. The lower insulatinglayer 105 may have a smaller thickness than the insulating layer 110.

The plurality of gate electrodes 300 may be stacked in the z directionperpendicular to the top of the substrate 100. The plurality of gateelectrodes 300 may be spaced apart from each other in the z direction bythe plurality of insulating layers 110 positioned between respectiveones of the plurality of gate electrodes 300.

A gate electrode 300G positioned on a lowermost end (e.g., closest tothe substrate 100) among the plurality of gate electrodes 300 may be aground selection line of the ground selection transistor GST describedwith reference to FIG. 1. A gate electrode 300S positioned on anuppermost end (e.g., farthest from the substrate 100) among theplurality of gate electrodes 300 may be a string selection line of thestring selection transistor SST described with reference to FIG. 1. Theplurality of gate electrodes 300 positioned between the gate electrode300G at the lowermost end and the gate electrode 300S at the uppermostend may be the word lines of the memory cell transistors MCx describedwith reference to FIG. 1.

The plurality of gate electrodes 300 may include doped silicon, metal(e.g., tungsten, copper, and/or aluminum), metal nitride (e.g., titaniumnitride, tantalum nitride, and the like), metal silicide, or acombination thereof. The plurality of insulating layers 110 may includea silicon oxide layer.

A lower semiconductor pattern 140 may protrude from the top of thesubstrate 100. The substrate 100 may include a recess region depressedfrom the top of the substrate 100 and the lower semiconductor pattern140 may be positioned to protrude on the top of the substrate 100 fromthe recess region. The lower semiconductor pattern 140 may protrude fromthe substrate 100 so as to penetrate the lower insulating layer 105 andthe gate electrode 300G positioned at the lowermost end among theplurality of gate electrodes 300. The lower semiconductor pattern 140may partially penetrate the insulating layer 110 positioned on the gateelectrode 300G positioned at the lowermost end among the plurality ofgate electrodes 300. The top of the lower semiconductor pattern 140 maybe positioned at a level between the bottom and the top of theinsulating layer 110 positioned on the gate electrode 300G positioned atthe lowermost end among the plurality of gate electrodes 300.

A gate insulating layer GI may be positioned between the lowersemiconductor pattern 140 and the gate electrode 300G positioned at thelowermost end. The gate insulating layer GI may be an oxide layer formedby performing an oxidation process in the lower semiconductor pattern140 of which an exterior surface is exposed during a manufacturingprocess. In some embodiments, the gate insulating layer GI may beoptional.

The lower semiconductor pattern 140 may be a semiconductor havingconductivity (for example, a p type) such as the substrate 100 or anintrinsic semiconductor. The lower semiconductor pattern 140 may beformed by using the substrate 100 as a seed. In some embodiments, thelower semiconductor pattern 140 may contain a single crystal structureor polycrystalline structure semiconductor material. As one example, thelower semiconductor pattern 140 may include silicon.

Since the lower semiconductor pattern 140 may be formed by performing anepitaxial growth (SEG) process using the semiconductor material, thetops of the lower semiconductor patterns 140 may have a curvature whichis not 0 (zero). The lower semiconductor pattern 140 may have the topwhich is convex upward. In detail, the plane (e.g., xy-direction plane)of the lower semiconductor pattern 140 may include an upper part 140_UPof which a width decreases as the distance from the substrate 100increases (e.g., toward the z direction) and a lower part 140_LPpositioned below the upper part 140_UP. In some embodiments, asillustrated in FIG. 2B, an upper surface of the upper part 140_UP of thelower semiconductor pattern 140 may incline upwards from an outer edgeof the upper part 140_UP (e.g. an edge closest to the stacked structureSS) away from the substrate 100. The lower part 140_LP may have asubstantially uniform width.

The lower semiconductor pattern 140 may include a first recess regionRS1 within the upper part 140_UP. A yz-direction cross section of thefirst recess region RS1 may have a curve-shaped profile. The firstrecess region RS1 may have a concave curve-shaped profile in which awidth decreases toward the substrate 100.

A plurality of vertical pattern structures VS may be connected with thelower semiconductor pattern 140 by penetrating the stacking structureSS. The vertical pattern structures VS may be arranged in the xdirection on the xy-direction plane. For example, the vertical patternsstructures VS may be arranged in zigzag in the x direction, but thepresent inventive concepts are not limited thereto. Further, thevertical pattern structures VS may be surrounded by the stackingstructure SS in the xy-direction plane.

Each of the vertical pattern structures VS may include a verticalchannel pattern 220 connected with the lower semiconductor pattern 140,a vertical insulating pattern 210 positioned between the verticalchannel pattern 220 and the stacking structure SS, and a fillinginsulating pattern 230 within and/or filling an inner region of thevertical channel pattern 220.

A conductive pad 240 may be connected to the vertical pattern structureVS by penetrating the stacking structure SS. The top of the conductivepad 240 may be substantially coplanar with the top of the stackingstructure SS and the bottom of the conductive pad 240 may directlycontact the vertical pattern structure VS. The conductive pad 240 mayinclude doped polysilicon and/or metal.

The bit line BTL crossing a capping layer 245 and the stacking structureSS may be positioned on the stacking structure SS. The bit line BTL maybe connected with the conductive pad 240 through a bit line contact 315penetrating the capping layer 245.

Referring to FIG. 2B, the vertical insulating pattern 210 may include ablocking insulating layer BL, a charge storing layer CL, and a tunnelinsulating layer TL sequentially stacked on the inner surface of thestacking structure SS.

The blocking insulating layer BL may directly contact the inner surface(e.g., one side wall) of the plurality of gate electrodes 300 and theplurality of insulating layers 110 and directly contact the upper part140_UP of the lower semiconductor pattern 140. In some embodiments, theblocking insulating layer BL may not contact the first recess region RS1in the upper part 140_UP of the lower semiconductor pattern 140. Thetunnel insulating layer TL may directly contact an outer surface of thevertical channel pattern 220 while surrounding the outer periphery ofthe vertical channel pattern 220.

In some embodiments, the charge storing layer CL may include at leastone of a silicon nitride layer, a silicon oxynitride layer, a silicon(Si)-rich nitride layer, nanocrystalline silicon (Si), and a laminatedtrap player. The tunnel insulating layer TL may contain a materialhaving a larger band gap than the charge storing layer CL. In someembodiments, the tunnel insulating layer TL may be a silicon oxidelayer. The blocking insulating layer BL may contain a material having alarger energy band gap than the charge storing layer CL. In someembodiments, the blocking insulating layer BL may be a silicon oxidelayer, a silicon oxynitride layer, an aluminum oxide layer, and/or ahafnium oxide layer.

The blocking insulating layer BL may include a vertical part BL_V whichextends in the z direction and a protrusion BL_P which extends towardthe vertical channel pattern 220 from the bottom of the vertical partBL_V. The protrusion BL_P of the blocking insulating layer BL maydirectly contact the top of the upper part 140_UP of the lowersemiconductor pattern 140. In some embodiments, the protrusion BL_P ofthe blocking insulating layer BL may not contact the first recess regionRS1 in the upper part 140_UP of the lower semiconductor pattern 140. Insome embodiments, the protrusion BL_P of the blocking insulating layerBL may be inclined on the top of the upper part 140_UP of the lowersemiconductor pattern 140. In detail, the protrusion BL_P of theblocking insulating layer BL may have a profile in which the protrusionBL_P is inclined away from the substrate 100 toward the vertical channelpattern 220 from a part connected with the vertical part BL_V.

The charge storing layer CL may include a vertical part CL_V whichextends in the z direction and a protrusion CL_P which extends towardthe vertical channel pattern 220 from the bottom of the vertical partCL_V. The bottom of the protrusion CL_P of the charge storing layer CLmay directly contact the top of the protrusion BL_P of the blockinginsulating layer BL. The protrusion CL_P of the charge storing layer CLmay have a profile in which the protrusion CL_P is inclined along theprotrusion BL_P of the blocking insulating layer BL. In detail, theprotrusion CL_P of the charge storing layer CL may have a profile inwhich the protrusion CL_P is inclined away from the substrate 100 towardthe vertical channel pattern 220 from a part connected with the verticalpart CL_V.

The tunnel insulating layer TL may include a vertical part TL_V whichextends in the z direction. The bottom of the vertical part TL_V of thetunnel insulating layer TL may directly contact the top of theprotrusion CL_P of the charge storing layer CL. The bottom of thevertical part TL_V of the tunnel insulating layer TL may have a profilein which the bottom is inclined like the top of the protrusion CL_P ofthe charge storing layer CL. In this case, the tunnel insulating layerTL does not substantially include the protrusion like the charge storinglayer CL and the blocking insulating layer BL.

The inner surface (e.g. the surface closest to the vertical channelpattern 220) of the protrusion BL_P of the blocking insulating layer BL,the inner surface of the protrusion CL_P of the charge storing layer CL,and the inner surface of the vertical part TL_V of the tunnel insulatinglayer TL may be substantially coplanar. The blocking insulating layerBL, the charge storing layer CL, and the tunnel insulating layer TL maybe etched in the same process so that edges of the respective layers aresubstantially coplanar.

The vertical channel pattern 220 may be positioned on the lowersemiconductor pattern 140 and may have a pipe shape in which one end isclosed, a hollow cylindrical shape in which one end is closed, or a cupshape, though the present inventive concepts are not limited thereto.

An upper part 220_UP of the vertical channel pattern 220 may have thepipe shape in which the upper part 220_UP directly contacts the innersurface of the tunnel insulating layer TL. A lower part 220_LP of thevertical channel pattern 220 may have the cup shape in which the lowerpart 220_LP directly contacts the lower semiconductor pattern 140 bypenetrating the tunnel insulating layer TL, the charge storing layer CL,and the blocking insulating layer BL.

The lower part 220_LP of the vertical channel pattern 220 may contactthe upper part 140_UP of the lower semiconductor pattern 140. In someembodiments, the bottom of the lower part 220_LP of the vertical channelpattern 220 may contact the upper part 140_UP of the lower semiconductorpattern 140 in the first recess region RS1. The first recess region RS1may have a curve shape, and the outer surface of the lower part 220_LPof the vertical channel pattern 220 contacting the first recess regionRS1 may have the curve shape. The vertical channel pattern 220 maycontact the lower semiconductor pattern 140 along the curve.

A lowermost end of the lower part 220_LP of the vertical channel pattern220 may be positioned at a higher level (e.g. farther from the substrate100) than the top of the gate electrode 300G positioned at the lowermostend of the plurality of gate electrodes 300. A distance from thelowermost end of the lower part 220_LP of the vertical channel pattern220 to the substrate 100 may be larger than a distance from the top ofthe gate electrode 300G positioned at the lowermost end to the substrate100.

The outer surface of the lower part 220_LP of the vertical channelpattern 220 may contact the inner surface of the vertical part TL_V ofthe tunnel insulating layer TL, the inner surface of the protrusion CL_Pof the charge storing layer CL, and the inner surface of the protrusionBL_P of the blocking insulating layer BL.

The lower part 220_LP of the vertical channel pattern 220 may have aprofile in which the width decreases toward the substrate 100. Since theouter surface of the lower part 220_LP of the vertical channel pattern220 directly contacts the first recess region RS1, the outer surface mayhave a curve profile corresponding to the first recess region RS1.

Further, as illustrated in FIG. 2C, the edge of the outer surface of thexy-direction cross section of the vertical channel pattern 220 and theedge of the inner surface of the xy-direction cross section of thevertical insulating pattern 210 may match each other. In particular, theedge of the outer surface of the xy-direction cross section of thevertical channel pattern 220 and the edge of the inner surface of thexy-direction cross section of the tunnel insulating layer TL may matcheach other. This may be due to the fact that the shape of the verticalchannel pattern 220 vertically has the same thickness throughout theupper and lower parts of the vertical channel pattern 220 and the tunnelinsulating layer TL in the vertical insulating pattern 210 does notinclude a separate protrusion.

The vertical channel pattern 220 may be a single layer having the samethickness t1 throughout the upper part 220_UP and the lower part 220_LP.Since the vertical channel pattern 220 may have a relatively smallthickness t1, a grain boundary in the vertical channel pattern 220 maybe reduced. When the grain boundary of the vertical channel pattern 220is reduced, a movement path of electrons may be shortened and a trapsite may also be reduced. Consequently, electron mobility of the channelmay increase, and, as a result, electrical characteristics (e.g., anoperation speed) of the device may be improved.

The vertical channel pattern 220 may include single crystal silicon,polycrystalline silicon, and/or amorphous silicon. In some embodiments,the vertical channel pattern 220 may be in an undoped state or be dopedwith impurities having the same conductive type as the substrate 100.The vertical channel pattern 220 may include a semiconductor materialhaving a polycrystalline structure or a single crystal structure. Insome embodiments, the vertical channel pattern 220 may include silicon.

The filling insulating pattern 230 may fill the inside of the verticalchannel pattern 220. The filling insulating pattern 230 may include aninsulating material such as silicon oxide, silicon oxynitride, and/orsilicon nitride.

The filling insulating pattern 230 may directly contact the innersurface of the vertical channel pattern 220. The lower part of thefilling insulating pattern 230 may have the profile in which the widthdecreases closer to the substrate 100 similarly to the lower part 220_LPof the vertical channel pattern 220.

Hereinafter, a semiconductor memory device according to another exampleembodiment of the present inventive concepts will be described withreference to FIGS. 3A and 3B. FIG. 3A is a perspective view illustratinga part of a semiconductor memory device according to another exampleembodiment of the present inventive concepts and FIG. 3B is an enlargeddiagram of region A of FIG. 3A. Detailed description of technicalfeatures that are duplicated with the technical features described withreference to FIGS. 1, 2A, and 2B herein will be omitted, and thedescription will primarily focus on differences between the exampleembodiments.

Referring to FIGS. 3A and 3B, the lower semiconductor pattern 140 mayinclude a concave top in which the center is lower (e.g., closer to thesubstrate 100) than the edge and the first recess region RS1 may definethe concave top. Therefore, an upper surface of the upper part 140_UP ofthe lower semiconductor pattern 140 may incline downwards from an outeredge of the upper part 140_UP (e.g. an edge farthest from the verticalchannel pattern 220) towards the substrate 100. In the present inventiveconcepts, a shape in which the top of the lower semiconductor pattern140 is convex up or concave down is illustrated, but is not limitedthereto and a flat shape may also be provided.

The edge of the lower semiconductor pattern 140 may be positioned at ahigher level than the bottom of the first recess region RS1. A distancefrom the edge of the upper part 140_UP of the lower semiconductorpattern 140 to the substrate 100 may be larger than the distance fromthe lowermost end of the first recess region RS1 to the substrate 100.

The blocking insulating layer BL may include a vertical part BL_V whichextends in the z direction and a protrusion BL_P which extends towardthe vertical channel pattern 220 from the bottom of the vertical partBL_V. The protrusion BL_P of the blocking insulating layer BL maydirectly contact the top of the upper part 140_UP of the lowersemiconductor pattern 140. In some embodiments, the protrusion BL_P maynot contact the first recess region RS1. The protrusion BL_P of theblocking insulating layer BL may have a profile in which the protrusionBL_P is inclined on the top of the upper part 140_UP of the lowersemiconductor pattern 140. In more detail, the protrusion BL_P may havea profile in which the protrusion BL_P is inclined toward the substrate100 in a direction toward the vertical channel pattern 220 from a partconnected with the vertical part BL_V.

The charge storing layer CL may include a vertical part CL_V whichextends in the z direction and a protrusion CL_P which extends towardthe vertical channel pattern 220 from the bottom of the vertical partCL_V. In detail, the protrusion CL_P may have a profile in which theprotrusion CL_P is inclined toward the substrate 100 in a directiontoward the vertical channel pattern 220 from a part connected with thevertical part CL_V.

The bottom of the vertical part TL_V of the tunnel insulating layer TLmay directly contact the top of the protrusion CL_P of the chargestoring layer CL. The bottom of the vertical part my of the tunnelinsulating layer TL may have a profile in which the bottom is inclinedlike the top of the protrusion CL_P of the charge storing layer CL.

The bottom of the lower part 220_LP of the vertical channel pattern 220may be positioned at a lower level than the edge of the lowersemiconductor pattern 140 farthest from the substrate 100 and may bepositioned at a higher level than the top of the gate electrode 300Gpositioned at the lowermost end of the plurality of gate electrodes 300.In other words, the distance from the lowermost end of the lower part220_LP of the vertical channel pattern 220 to the substrate 100 may besmaller than the distance from the upper edge of the lower semiconductorpattern 140 to the substrate 100 and larger than the distance from thetop of the gate electrode 300G positioned at the lowermost end to thesubstrate 100.

In some embodiments, as illustrated in FIGS. 3A and 3B, the gateinsulating layer GI may be omitted from between the between the lowersemiconductor pattern 140 and the gate electrode 300G positioned at thelowermost end of the plurality of gate electrodes 300.

Hereinafter, a semiconductor memory device according to another exampleembodiment of the present inventive concepts will be described withreference to FIGS. 4A and 4B. FIG. 4A is a perspective view illustratinga part of a semiconductor memory device according to another exampleembodiment of the present inventive concepts and FIG. 4B is an enlargeddiagram of region A of FIG. 4A. Detailed description of technicalfeatures that are duplicated with technical features described withreference to FIGS. 1, 2A, and 2B as above will be omitted, and thedescription will primarily focus on differences between the exampleembodiments.

Referring to FIGS. 4A and 4B, the lower semiconductor pattern 140 mayinclude the first recess region RS1 penetrating the upper part 140_UP.The yz-direction cross section of the first recess region RS1 may have aprofile having a shape including an uneven surface. The first recessregion RS1 may substantially have a profile in which the width decreasestoward the substrate 100.

The outer surface of the lower part 220_LP of the vertical channelpattern 220 may include an irregularly uneven surface. In detail, alateral surface of the protrusion BL_P of the blocking insulating layerBL directly contacting the outer surface of the lower part 220_LP of thevertical channel pattern 220, the lateral surface of the protrusion CL_Pof the charge storing layer CL, and the inner surface of the verticalpart TL_V of the tunnel insulating layer TL may not form a coplanarsurface, but form an uneven surface.

In the vertical channel pattern 220 connected with the lowersemiconductor pattern 140, the first thickness t1 of the yz-directioncross section of the upper part 220_UP of the vertical channel pattern220 and a second thickness t2 of the yz-direction cross section of thelower part 220_LP may be different from each other. In detail, thesecond thickness t2 may be larger than the first thickness t1.

A lower surface of the filling insulating pattern 230 may have an unevenshape. The lower surface of the filling insulating pattern 230 may beformed on the surface of the vertical channel pattern 220 while directlycontacting the surface of the vertical channel pattern 220.

Hereinafter, manufacturing methods of semiconductor memory devicesaccording to example embodiments of the present inventive concepts willbe described with reference to FIGS. 5 to 20. FIGS. 5, 6, 7, 8, 9A, 10A,11A, 12A, 13A, 14A, 15, 16, 17, 18, 19, and 20 are cross-sectional viewsfor describing the manufacturing methods of the 3D semiconductor memorydevices according to example embodiments of the present inventiveconcepts and each of FIGS. 9B, 10B, 11B, 12B, 13B, and 14B are enlargeddiagrams of region A of the corresponding figures according to themanufacturing methods.

Referring to FIG. 5, the plurality of insulating layers 110 and aplurality of sacrificial layers 120 are stacked on the substrate 100alternately in the z direction.

The plurality of sacrificial layers 120 may have substantially the samethickness. However, the present inventive concepts are not limitedthereto, and the sacrificial layers 120 of a lowermost part and anuppermost part of the stacked plurality of sacrificial layers 120 may beformed to be thicker than other sacrificial layers 120 positionedtherebetween. In some embodiments, the plurality of insulating layers110 may have substantially the same thickness, but in some embodimentsthe insulating layer 110 positioned in the lowermost part and theuppermost part of the stacked plurality of the insulating layers 110 mayhave different thicknesses than other insulating layers 110 positionedtherebetween.

The plurality of sacrificial layers 120 may include a silicon nitridelayer, a silicon oxynitride layer, and/or a silicon layer and theplurality of insulating layers 110 may include a silicon oxide layer.The plurality of sacrificial layers 120 and the plurality of insulatinglayers 110 may be deposited by using a thermal CVD, plasma enhanced CVD,physical CVD, or atomic layer deposition (ALD) process, though thepresent inventive concepts are not limited thereto.

In addition, the lower insulating layer 105 may be formed between thesubstrate 100 and the sacrificial layer 120 positioned at the lowermostend. The lower insulating layer 105 may be made of a material having ahigher selection ratio than the plurality of sacrificial layers 120 andthe plurality of insulating layers 110. As one example, the lowerinsulating layer 105 may include a high dielectric layer such as asilicon nitride layer, an aluminum oxide layer, and/or a hafnium oxidelayer. The lower insulating layer 105 may be formed to have a smallerthickness than the plurality of sacrificial layers 120 and the pluralityof insulating layers 110.

Referring to FIG. 6, a channel hole 130 may be formed, which exposes thesubstrate 100 by penetrating the plurality of insulating layers 110 andthe plurality of sacrificial layers 120 in a direction (e.g., the zdirection) perpendicular to the substrate 100. In some embodiments,forming the channel hole 130 may include forming a mask pattern (notillustrated) on the insulating layer 110 positioned in the uppermostpart and anisotropically etching the insulating layers 110, thesacrificial layers 120, and the lower insulating layer 105 until the topof the substrate 100 is exposed by using the mask pattern (notillustrated) as an etching mask. In an anisotropic etching process, thetop of the substrate 100 in the channel hole 130 may be recessed with apredetermined depth by overetching. Thereafter, the mask pattern may beremoved.

As illustrated in FIG. 6, the channel hole 130 may be formed to have auniform width according to a height from the substrate 100 by theanisotropic etching, but the present inventive concepts are not limitedthereto, and the channel hole 130 may be formed to have a differentwidth according to the height from the substrate 100. That is, thechannel hole 130 may have a side wall inclined to the substrate 100. Thechannel hole 130 may have a circular shape, oval shape, or polygonalshape from the viewpoint of a plane parallel to the substrate (e.g., anx-y plane).

Next, as illustrated in FIG. 7, a lower semiconductor layer LSL withinand/or filling the recessed region may be formed. The lowersemiconductor layer LSL may be formed by performing a selectiveepitaxial growth (SEG) process using the substrate 100 exposed by thechannel hole 130 as a seed. The lower semiconductor layer LSL may beintegrated with the substrate 100.

The lower semiconductor layer LSL may be formed in a pillar shape inwhich the lower semiconductor layer LSL protrudes from the top of thesubstrate 100 in the z direction to fill a lower region of the channelhole 130. The lower semiconductor layer LSL may cover the side wall ofthe sacrificial layer 120 in the lowermost part of the plurality ofsacrificial layers 120. The top of the lower semiconductor layer LSL maybe positioned at a level between the bottom and the top of theinsulating layer 110 on the lowermost sacrificial layer 120 of theplurality of sacrificial layers 120. The distance from the uppermostpart of the lower semiconductor layer LSL to the substrate 100 may belarger than the distance from the top of the sacrificial layer 120positioned at the lowermost end to the substrate 100.

As a result of performing the selective epitaxial growth process, eachlower semiconductor layer LSL may have the top which is convex up. Indetail, the width of the upper part of the lower semiconductor layer LSLmay decrease in the z direction away from the substrate 100.

The lower semiconductor layer LSL may include the same conductivesemiconductor material as the substrate 100. In the selective epitaxialgrowth process, the lower semiconductor layer LSL may be doped with theimpurities in-situ. The lower semiconductor layer LSL may include asingle-crystal structure and/or polycrystalline structure semiconductormaterial and, in some embodiments, the lower semiconductor layer LSL mayinclude silicon.

Next, as illustrated in FIG. 8, after the selective epitaxial growthprocess, an ion injection process may be performed with respect to a topsurface of the substrate 100 including the lower semiconductor layerLSL. The lower semiconductor layer LSL may include a first region LSL1including a first impurity through the ion injection process. The firstimpurity may be at least one of C, N, O, Cl, F, B, Ph, and As. Amongthem, C, N, O, and Cl may be more appropriate. The first region LSL1 maybe formed in the upper part of the lower semiconductor layer LSL. Indetail, the first region LSL1 may be formed at a higher level than thetop of the sacrificial layer 120 positioned at the lowermost end.

Meanwhile, the lower semiconductor layer LSL may be doped with theimpurities in the selective epitaxial growth process. In someembodiments, the doped impurities may be a second impurity and a secondregion LSL2 including a second impurity may be formed. The secondimpurity may be the same conductive impurity as the substrate 100.

When the first impurity is injected through the ion injection process,the first impurity may form a profile in which the first impurity iscontinuous or discontinuous in the lower semiconductor layer LSL andamong them, the first region LSL1 may include a region in which thefirst impurity is distributed most. Similarly thereto, the second regionLSL2 may include a region in which the second impurity is distributedmost among regions doped with the second impurity.

The first region LSL1 may be positioned in the upper part of the lowersemiconductor layer LSL and the second region LSL2 may be positioned inthe lower part of the lower semiconductor layer LSL, and the level ofthe first region LSL1 may be higher than the level of the second regionLSL2. In other words, the distance from the first region LSL1 to thesubstrate 100 may be larger than the distance from the second regionLSL2 to the substrate 100.

Further, the first region LSL1 may be formed to be positioned at ahigher level than the top of the sacrificial layer 120 positioned at thelowermost end, and the second region LSL2 may be formed to be positionedat substantially the same level as the sacrificial layer 120 positionedat the lowermost end. That is, the distance from the first region LSL1to the substrate 100 may be larger than the distance from the top of thesacrificial layer 120 positioned at the lowermost end to the substrate100 and the second region LSL2 may overlap with the sacrificial layer120 positioned at the lowermost end in the y direction.

Meanwhile, the ion injection process is performed with respect to thetop surface of the substrate 100, and as a result, the first impuritymay be injected into the insulating layer 110 positioned at theuppermost end as well as the lower semiconductor layer LSL. Accordingly,the insulating layer 110 positioned at the uppermost end may include thefirst impurity.

Referring to FIG. 9A, a vertical insulating layer 210 a may be formed,which is on the inner wall of the channel hole 130 and is on the top ofthe lower semiconductor layer LSL. The channel hole 130 may not becompletely filled by the vertical insulating layer 210 a. The lower partof the vertical insulating layer 210 a may have a profile in which thelower part is inclined on the top of the lower semiconductor layer LSL.In detail, the lower part of the vertical insulating layer 210 a mayhave a shape in which the lower part is inclined away from the substrate100 toward the center of the lower semiconductor layer LSL.

Forming the vertical insulating layer 210 a may include sequentiallyconformally forming the blocking insulating layer BL, the charge storinglayer CL, and the tunnel insulating layer TL on the inner wall of thechannel hole 130 as illustrated in FIG. 9B. In some embodiments, theblocking insulating layer BL may include a silicon oxide layer, asilicon oxynitride layer, an aluminum oxide layer, and/or a hafniumoxide layer. The charge storing layer CL may include at least one of asilicon nitride layer, a silicon oxynitride layer, a silicon (Si)-richnitride layer, a nanocrystalline silicon (Si), and/or a laminated traplayer. The tunnel insulating layer TL may include a silicon oxide layer.Each of the blocking insulating layer BL, the charge storing layer CL,and the tunnel insulating layer TL may be deposited by using the plasmaenhanced CVD, physical CVD, or atomic layer deposition (ALD) process,though the present inventive concepts are not limited thereto.

Referring to FIGS. 10A and 10B, a sacrificial channel layer 220 a may beformed in the channel hole 130. The sacrificial channel layer 220 a maybe formed on the vertical insulating layer 210 a. The sacrificialchannel layer 220 a may include a single crystal silicon, apolycrystalline silicon, and/or an amorphous silicon. The sacrificialchannel layer 220 a may be formed by using the atomic layer deposition(ALD) or chemical vapor deposition (CVD), though the present inventiveconcepts are not limited thereto.

The sacrificial channel layer 220 a may be formed to cover the innersurface of the vertical insulating layer 210 a. In some embodiments, thechannel hole 130 may not be completely filled by the sacrificial channellayer 220 a. The lower part of the sacrificial channel layer 220 a mayhave a profile in which the lower part is inclined away from thesubstrate 100 toward the center of the lower semiconductor layer LSLalong the lower part of the vertical insulating layer 210 a.

Next, a vertical insulating intermediate pattern 210 b and a sacrificialchannel pattern 220 b may be formed in the channel hole 130 byanisotropically etching the sacrificial channel layer 220 a and thevertical insulating layer 210 a as illustrated in FIG. 11A. Each of thevertical insulating intermediate pattern 210 b and the sacrificialchannel pattern 220 b may have a pipe shape in which the top and thebottom are opened. The vertical insulating intermediate pattern 210 band the sacrificial channel pattern 220 b may expose a part of a lowersemiconductor intermediate pattern LSL_a formed by partially etching thelower semiconductor layer LSL.

In detail, referring to FIG. 11B, the vertical insulating intermediatepattern 210 b may be formed to include the blocking insulating layer BLincluding the vertical part BL_V and the protrusion BL_P which extendsfrom the vertical part BL_V toward the channel hole 130, the chargestoring layer CL including the vertical part CL_V and the protrusionCL_P which extends from the vertical part CL_V toward the channel hole130, and the tunnel insulating layer TL including the vertical part TL_Vand the protrusion TL_P which extends from the vertical part TL_V towardthe channel hole 130. In some embodiments, the inner surfaces of theprotrusions BL_P, CL_P, and TL_P included in the blocking insulatinglayer BL, the charge storing layer CL, and the tunnel insulating layerTL, respectively are etched through the same process, and as a result,the inner surfaces may form the same (e.g. coplanar) surface.

The sacrificial channel pattern 220 b may be removed in such a mannerthat the bottom which overlaps with the top of the lower semiconductorlayer LSL which protrudes is removed. The sacrificial channel pattern220 b may be formed by removing the sacrificial channel layer 220 awhich overlaps with the bottom of the channel hole 130. The sacrificialchannel pattern 220 b may directly contact the vertical part TL_V of thetunnel insulating layer TL and may not contact the blocking insulatinglayer BL and the charge storing layer CL.

Further, as a result of the overetching while anisotropically etchingthe sacrificial channel layer 220 a and the vertical insulating layer210 a, the lower semiconductor intermediate pattern LSL_a may include anintermediate recess region RS_a which is recessed concavely toward thesubstrate 100. The level of the lowermost end of the intermediate recessregion RS_a may be formed to be higher than the level of the top of thesacrificial layer 120 positioned at the lowermost end of the pluralityof sacrificial layers 120.

Next, as illustrated in FIG. 12A, the sacrificial channel pattern 220 bmay be completely removed and the lower semiconductor intermediatepattern LSL_a which overlaps with the sacrificial channel pattern 220 bmay be partially etched to form the lower semiconductor pattern 140including the first recess region RS1.

As a solution that etches the sacrificial channel pattern 220 b,alkaline solutions such as, for example, an ammonia solution, potassiumhydroxide, or tetramethylammonium hydroxide (TMAH) may be used and/or anetching atmosphere may adopt gas such as, for example, NF₃, Cl₂, andHBr.

In the course of etching the sacrificial channel pattern 220 b, thelower semiconductor intermediate pattern LSL_a may be overetched by theetching solution and/or patterned in a predetermined shape. However, thelower semiconductor pattern 140 according to example embodiments of thepresent inventive concepts may include the first region LSL1 doped withthe first impurity, and the first impurity included in the first regionLSL1 may have resistance to the etching solution to prevent the lowersemiconductor pattern 140 from being overetched. The first region LSL1may serve as an etching stopper, and as a result, the lowersemiconductor pattern 140 may be prevented or inhibited from beingrecessed to the first region LSL1 or lower. The first region LSL1included in the lower semiconductor pattern 140 may be exposed by theetching.

As illustrated in FIG. 12B, the edge of the first recess region RS1 maysubstantially match the edge of the outer surface of the sacrificialchannel pattern (see 220 b of FIG. 11B) which is removed.

Further, a part of the protrusion BL_P of the blocking insulating layerBL which overlaps with the sacrificial channel pattern (see 220 b ofFIG. 11B), a part of the protrusion CL_P of the charge storing layer CL,and the entirety of the protrusion TL_P (see FIG. 11B) of the tunnelinsulating layer TL are etched at the time of removing the sacrificialchannel pattern (see 220 b of FIG. 11B), and as a result, the blockinginsulating layer BL, the charge storing layer CL, and the tunnelinsulating layer TL illustrated in FIG. 12B may be formed. The innersurfaces of the protrusions BL_P and CL_P included in the blockinginsulating layer BL and the charge storing layer CL, respectively, andthe inner surface of the vertical part TL_V of the tunnel insulatinglayer TL may be configured to form the same (e.g., coplanar) surface.

Next, as illustrated in FIGS. 13A and 13B, a vertical channel layer 220c may be formed in the channel hole 130. The vertical channel layer 220c may be formed with a thickness so as not to completely fill thechannel hole 130, that is, a predetermined thickness in the channel hole130.

The vertical channel layer 220 c may include a semiconductor materialhaving the polycrystalline structure or single crystal structure. Insome embodiments, the vertical channel layer 220 c may include apolycrystalline silicon layer, a single-crystal silicon layer, and/or anamorphous silicon layer. The vertical channel layer 220 c may be formedby using the atomic layer deposition (ALD) or chemical vapor deposition(CVD), though the present inventive concepts are not limited thereto.

The thickness of the vertical channel layer 220 c may decrease byperforming a cleaning process on the vertical channel layer 220 c. Thecleaning process may be, as one example, a standard clean (SC)-1process. In the cleaning process, a mixed cleaning solution of ammoniumhydroxide and hydrogen peroxide may be used. During the cleaningprocess, a part of the vertical channel layer 220 c which is exposed maybe oxidized and, subsequently, the part of the vertical channel layer220 c which is oxidized may be removed. Accordingly, as a result of thecleaning process, the vertical channel layer 220 c may be formed to havethe first thickness t1.

Subsequently, as illustrated in FIGS. 14A and 14B, a filling insulatinglayer 230 a may be formed to be within and, in some embodiments,completely fill, the inside of the channel hole 130. The fillinginsulating layer 230 a may be a silicon oxide layer formed by using anSOG technology.

Thereafter, as illustrated in FIG. 15, the filling insulating pattern230 and the vertical channel pattern 220 filling the channel hole 130may be formed by performing a planarization process such as an etch-backprocess or a CMP process in the upper part of the insulating layer 110positioned at the uppermost end.

After the planarization process, the insulating layer 110 positioned atthe uppermost end may include the first impurity according to an ioninjection depth of the ion injection process performed in FIG. 8.

The vertical channel pattern 220 may be formed in the channel hole 130in the pipe shape in which one end (e.g., the end closest to the lowersemiconductor pattern 140) is closed, the hollow cylindrical shape inwhich one end is closed, or the cup shape. The filling insulatingpattern 230 may be formed in a pillar shape to be within and, in someembodiments, fill the inside of the channel hole 130 in which thevertical channel pattern 220 is formed. The vertical insulating pattern210, the vertical channel pattern 220, and the filling insulatingpattern 230 may constitute the vertical pattern structure VS.

In addition, the conductive pad 240 may be formed, which is connected tothe vertical pattern structure VS. The conductive pad 240 may be formedby filling a conductive material on the vertical pattern structure VSwhich is recessed based on the top of the insulating layer 110positioned in the uppermost part of the plurality of insulating layers110. In some embodiments, the conductive pad 240 may be made ofpolysilicon and/or metal doped with impurities having the sameconductive type as the substrate 100. As illustrated in FIG. 15, the topformed by the uppermost insulating layer 110, the vertical patternstructure VS, and the conductive pad 240 may be planarized.

As illustrated in FIG. 16, the capping layer 245 may be formed andthereafter, the capping layer 245, the insulating layers 110, thesacrificial layers 120, and the lower insulating layer 105 may beanisotropically etched between adjacent vertical pattern structures VS,and, as a result, a trench 250 may be formed. In detail, forming thetrench 250 may include forming a second mask pattern (not illustrated)defining a planar position where the trench 250 is to be formed in theplurality of insulating layers 110 and the plurality of sacrificiallayers 120, and etching the plurality of insulating layers 110 and theplurality of sacrificial layers 120 by using a second mask pattern as anetching mask. Thereafter, the second mask pattern may be removed.

The trench 250 may be formed to expose the side walls of the sacrificiallayers 120 and the insulating layers 110. In a vertical depth, thetrench 250 may be formed to expose the side wall of the lower insulatinglayer 105. Further, although not illustrated, the trench 250 may have adifferent width depending on the distance from the substrate 100 by theanisotropic etching process.

The trench 250 may extend in the x direction. The lateral surfaces ofthe capping layer 245, the insulating layers 110, the sacrificial layers120, and the lower insulating layer 105 may be exposed to the inner wallof the trench 250.

Next, as illustrated in FIG. 17, the sacrificial layer 120 exposed bythe trench 250 is selectively removed to form a gap 260 between theinsulating layers 110. The gap 260 may correspond to regions where thesacrificial layers 120 are removed. When the sacrificial layer 120includes the silicon nitride layer or the silicon oxynitride layer, theremoving process of the sacrificial layers 120 may be performed by usingthe etching solution including phosphoric acid. A part of the outersurface of the vertical pattern structure VS may be exposed by the gap260. Further, a part of the outer surface of the lower semiconductorpattern 140 may be exposed by the gap 260.

Next, as illustrated in FIG. 18, a gate electrode 300 filling the gap260 may be formed. In detail, a conductive layer may be formed to notcompletely fill the trench 250 while filling the gap 260. Thereafter,the plurality of gate electrodes 300 may be formed, which are positionedin the gap 260 by removing the conductive layer formed at the outside(e.g., within the trench 250) of the gap 260. The plurality of gateelectrodes 300 and the plurality of insulating layers 110 which arestacked may constitute the stacking structure SS.

In some embodiments, prior to forming the gate electrode 300, the gateinsulating layer GI may be formed between the lower semiconductorpattern 140 and the gate electrode 300G positioned at the lowermost end.The gate insulating layer GI may be formed by performing the oxidizationprocess on the outer surface of the lower semiconductor pattern 140exposed by the gap 260 (see FIG. 17). In some embodiments, the formationof the gate insulating layer GI may be omitted.

Next, as illustrated in FIG. 19, the common source region 280 may beformed on the substrate 100. The common source region 280 may be formedby an ion injection process in the substrate 100 exposed by the trench250. The common source region 280 may configure a PN junction with thesubstrate 100.

Next, a trench spacer 285 may be foamed on the side wall of the trench250 and the common source line CSL which extends in the x directionwhile filling the trench 250 may be formed. The common source line CSLmay be electrically connected by contacting the common source region280. The trench spacer 285 may electrically insulate the plurality ofgate electrodes 300 and the common source line CSL. The trench spacer285 may include an insulating material such as silicon oxide and/ornitride. The common source line CSL may include metallic materials suchas tungsten, titanium, tantalum, platinum, and/or metal silicide.

The bit line contact 315 which is connected to the conductive pad 240illustrated in FIG. 20 may be formed. The bit line contact 315 mayinclude metal such as tungsten and/or copper. Thereafter, the bit lineBTL which contacts the top of the bit line contact 315 and extends inthe y direction may be formed. The bit line BTL may include the metalsuch as the tungsten and/or copper.

Hereinafter, manufacturing methods of the semiconductor memory devicesaccording to other example embodiments of the present inventive conceptswill be described with reference to FIGS. 21A and 21B. Description ofthe same or similar processes as FIGS. 5 to 20 will be omitted.

First, the same manufacturing processes as FIGS. 5 to 7 are performed.

Thereafter, the lower semiconductor layer LSL may be doped with thesecond impurity. The second region LSL2 including the second impuritymay be formed in the lower semiconductor layer LSL. The second impuritymay be the same conductive impurity as the substrate 100.

Next, as illustrated in FIG. 9A, the vertical insulating layer 210 a maybe formed, which covers the inner wall of the channel hole 130 andcovers the top of the lower semiconductor layer LSL.

Thereafter, as illustrated in FIGS. 21A and 21B, the ion injectionprocess may be performed with respect to the top surface of thesubstrate 100 on the vertical insulating layer 210 a. The lowersemiconductor layer LSL may include a first region D including a firstimpurity through the ion injection process. The first impurity may be atleast one of C, N, O, Cl, F, B, Ph, and As. Among them, C, N, O, and Clmay be more appropriate.

The width of the first region D may be smaller than that of a secondregion LSL2. In FIG. 21A, when the ion injection process of the firstimpurity is performed with respect to the top surface of the substrate100, the first region D may be formed in a region which overlaps withthe channel hole 130. In some embodiments, the first region D may have awidth less than or equal to the width of the channel hole 130.

Meanwhile, the second region LSL2 may be formed by injecting a secondimpurity into the channel hole 130 in which the vertical insulatinglayer 210 a is not formed as illustrated in FIG. 8. The width of thesecond region LSL2 may substantially match the width of the channel hole130 according to FIG. 8.

Accordingly, the first region D may be formed to have a smaller widththan the second region LSL2.

Thereafter, the processes illustrated and described through FIGS. 10A to20 may be similarly performed.

Hereinafter, a semiconductor memory characteristic according to anexample embodiment and a comparative example will be described withreference to FIGS. 22 to 25. FIG. 22 is a diagram illustrating across-sectional shape of a lower semiconductor pattern according to anexample embodiment of the present inventive concepts and FIG. 23 is adiagram illustrating a cross-sectional shape of a lower semiconductorpattern according to a comparative example, FIG. 24 is a graphillustrating applied current to gate voltage applied to the exampleembodiment of FIG. 22 and the comparative example of FIG. 23, and FIG.25 is a graph illustrating a worst on-cell current characteristic.

According to the example embodiment, in the semiconductor memory deviceincluding the first region LSL1 doped with carbon C, the widest portionof the first recess region RS1 included in the lower semiconductorpattern 140 may have substantially the same diameter as the channel hole130 as illustrated in FIG. 22.

In the process of removing the sacrificial channel layer (see referencenumeral 220 a of FIG. 11A) contacting the vertical insulating pattern210, the etching solution removing the sacrificial channel layer mayetch even the lower semiconductor pattern 140 exposed by the channelhole 130. However, the semiconductor memory device according to theexample embodiment includes the first region LSL1, and as a result, theoveretching of the lower semiconductor pattern 140 by the etchingsolution may be prevented and the first recess region RS1 of the lowersemiconductor pattern 140 may form a plane having substantially the samesize as the channel hole 130 on which the vertical channel layer isdeposited afterwards. As a result, the channel may be stably formed inspite of the vertical channel pattern which is formed with a smallthickness.

However, the semiconductor memory device according to the comparativeexample, which does not include the first region LSL1 (see FIG. 22) mayoveretch the upper part of the lower semiconductor pattern 140 exposedby the etching solution used in the process of removing the sacrificialchannel layer as illustrated in FIG. 23. As a result, the lowersemiconductor pattern 140 of the comparative example includes a recessregion RS2 having a larger diameter at its widest point than the channelhole 130, and when the vertical channel layer is deposited on the recessregion RS2, there is a high possibility that the channel will bedisconnected between the lower semiconductor pattern 140 and thevertical insulating pattern 210 and reliability of the device maydeteriorate.

Meanwhile, FIG. 24 illustrating the current which flows according to theapplied voltage illustrates that an on-off characteristic of a memorycell is excellent as a slope of the graph is large. According to FIG.24, it can be seen that the graph slope of the semiconductor memorydevice according to the example embodiment is formed to be larger thanthe graph slope of the semiconductor memory device according to thecomparative example. The semiconductor memory device according to theexample embodiment of the present inventive concepts includes the firstregion LSL1, and as a result, it can be seen that the on-offcharacteristic of the semiconductor memory device including the stablevertical channel pattern is improved as compared with the comparativeexample.

Further, the graph regarding the worst on-cell current characteristicillustrated in FIG. 25 is a graph illustrating current which flows inthe corresponding cell at the time of applying the same voltage.Referring to the graph, it can be seen that the example embodiment has ahigher current value than the comparative example when voltage isapplied to each memory cell. This means that higher current may flow inthe memory cell according to the example embodiment when the samevoltage is applied to each memory cell, and as a result, it can be seenthat an electrical characteristic of the semiconductor memory devicesaccording to the present inventive concepts are improved.

Hereinafter, an electronic system and a memory card including thesemiconductor memory device will be, in brief, described with referenceto FIGS. 26 and 27. FIG. 26 is a block diagram schematicallyillustrating one example of an electronic system including asemiconductor memory device according to example embodiments of thepresent inventive concepts and FIG. 27 is a block diagram schematicallyillustrating one example of a memory card including a semiconductormemory device according to example embodiments of the present inventiveconcepts.

Referring to FIG. 26, the electronic system 1100 according to theexample embodiment of the present inventive concepts may include acontroller 1110, an input/output device (I/O) 1120, a memory device1130, an interface 1140, and a bus 1150. At least two of the controller1110, the input/output device 1120, the memory device 1130, and theinterface 1140 may be coupled with each other through the bus 1150. Thebus 1150 may correspond to a path where data moves.

The controller 1110 may include at least one of a microprocessor, adigital signal processor, a microcontroller, and/or logic devicescapable of performing similar functions thereto. The input/output device1120 may include a keypad, a keyboard, and/or a display device. Thememory device 1130 may store data and/or commands. The memory device1130 may include the semiconductor memory device disclosed in theaforementioned example embodiments. The memory device 1130 may furtherinclude at least one of a phase-change memory device, a magnetic memorydevice, a DRAM device, and/or an SRAM device. The interface 1140 mayperform a function to transmit the data to a communication networkand/or receive the data from the communication network. The interface1140 may be a wired and/or wireless type. For example, the interface1140 may include an antenna and/or a wired/wireless transceiver.Although not illustrated, the electronic system 1100 may include amemory device for improving an operation of the controller 1110, and mayfurther include at least one of a high-speed DRAM device and/or ahigh-speed SRAM device.

The electronic system 1100 may be applied to a personal digitalassistant (PDA), a portable computer, a web tablet, a wireless phone, amobile phone, a digital music player, a memory card, and/or andelectronic products which may transmit and receive information in awireless environment.

Referring to FIG. 27, a memory card 1200 according to the exampleembodiments of the present inventive concepts may include a memorydevice 1210. The memory device 1210 may include the semiconductor memorydevice according to the aforementioned example embodiments. The memorydevice 1210 may further include at least one of the phase-change memorydevice, the magnetic memory device, the DRAM device, and/or the SRAMdevice. The memory card 1200 may include a memory controller 1220 whichcontrols data exchange between a host and the memory device 1210.

The memory controller 1220 may include a processing unit 1222 thatcontrols operations of the memory card. Further, the memory controller1220 may include an SRAM 1221 used as an operation memory of theprocessing unit 1222. In addition, the memory controller 1220 mayfurther include a host interface 1223 and a memory interface 1225. Thehost interface 1223 may include a data exchange protocol between thememory card 1200 and the host. The memory interface 1225 may access thememory controller 1220 and the memory device 1210. Furthermore, thememory controller 1220 may further include an error correction block(ECC) 1224. The error correction block 1224 may detect and correct anerror of the data read from the memory device 1210. Although notillustrated, the memory card 1200 may further include a ROM devicestoring code data for interfacing with the host. The memory card 1200may be used as a portable data storage card. In some embodiments, thememory card 1200 may be implemented as a solid state disk (SSD) whichmay substitute for a hard disk of a computer system.

In the semiconductor memory device according to the present inventiveconcepts, the lower semiconductor pattern and the vertical channelpattern stably contact each other, and as a result, the reliability ofthe semiconductor memory device can be improved. Further, the memorycard or the electronic system may include the semiconductor memorydevice according to the example embodiments to improve an operatingspeed and electrical characteristics (e.g., noise resistance, and thelike) of a system.

It will be understood that although the terms “first,” “second,” etc.are used herein to describe members, regions, layers, portions,sections, components, and/or elements in example embodiments of theinventive concepts, the members, regions, layers, portions, sections,components, and/or elements should not be limited by these terms. Theseterms are only used to distinguish one member, region, portion, section,component, or element from another member, region, portion, section,component, or element. Thus, a first member, region, portion, section,component, or element described below may also be referred to as asecond member, region, portion, section, component, or element withoutdeparting from the scope of the inventive concepts. For example, a firstelement may also be referred to as a second element, and similarly, asecond element may also be referred to as a first element, withoutdeparting from the scope of the inventive concepts.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe the relationship of one element or feature to anotherelement(s) or feature(s) as illustrated in the figures. It will beunderstood that the spatially relative terms are intended to encompassdifferent orientations of the device in use or operation in addition tothe orientation depicted in the figures. For example, if the device inthe figures is turned over, elements described as “below” or “beneath”other elements or features would then be oriented “above” the otherelements or features. Thus, the exemplary term “below” can encompassboth an orientation of above and below. The device may be otherwiseoriented (rotated 90 degrees or at other orientations) and the spatiallyrelative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an,” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises,” “comprising,” “includes,” and/or “including,” if usedherein, specify the presence of stated features, integers, steps,operations, elements and/or components, but do not preclude the presenceor addition of one or more other features, integers, steps, operations,elements, components and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by thoseof ordinary skill in the art to which the inventive concepts pertain. Itwill also be understood that terms, such as those defined in commonlyused dictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of this specification andthe relevant art and will not be interpreted in an idealized or overlyformal sense unless expressly so defined herein.

When a certain example embodiment may be implemented differently, aspecific process order may be performed differently from the describedorder. For example, two consecutively described processes may beperformed substantially at the same time or performed in an orderopposite to the described order.

In the accompanying drawings, variations from the illustrated shapes asa result, for example, of manufacturing techniques and/or tolerances,are to be expected. Thus, the example embodiments of the inventiveconcepts should not be construed as being limited to the particularshapes of regions illustrated herein but may be construed to includedeviations in shapes that result, for example, from a manufacturingprocess. For example, an etched region illustrated as a rectangularshape may be a rounded or certain curvature shape. Thus, the regionsillustrated in the figures are schematic in nature, and the shapes ofthe regions illustrated in the figures are intended to illustrateparticular shapes of regions of devices and not intended to limit thescope of the present inventive concepts. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items. Expressions such as “at least one of,” whenpreceding a list of elements, modify the entire list of elements and donot modify the individual elements of the list.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Other words used to describe therelationship between elements or layers should be interpreted in a likefashion (e.g., “between” versus “directly between,” “adjacent” versus“directly adjacent,” “on” versus “directly on”).

Like numbers refer to like elements throughout. Thus, the same orsimilar numbers may be described with reference to other drawings evenif they are neither mentioned nor described in the correspondingdrawing. Also, elements that are not denoted by reference numbers may bedescribed with reference to other drawings.

Although the example embodiments of the present inventive concepts havebeen described with reference to the accompanying drawings as describedabove, those skilled in the art will be able to understand that thepresent inventive concepts can be implemented in other detailed formswithout changing the technical spirit or an essential characteristic.Therefore, it should be understood that the aforementioned exampleembodiments are illustrative in terms of all aspects and are notlimited. Accordingly, the scope of the present inventive concepts shouldbe determined as a widest scope of permissible analysis from theappended claims and equivalents thereto.

DESCRIPTION OF SYMBOLS

-   -   100: Substrate    -   110: Insulation layer    -   140: Lower semiconductor pattern    -   210: Vertical insulating pattern    -   220: Vertical channel pattern    -   300: Memory cell gate electrode    -   300S: String selection transistor gate electrode    -   300G: Ground selection transistor gate electrode    -   RS1: First recess region

1.-9. (canceled)
 10. A method for manufacturing a semiconductor memorydevice, comprising: forming a stacking structure by alternately stackinga plurality of insulating layers and a plurality of sacrificial layerson a substrate; forming a channel hole by penetrating the plurality ofinsulating layers and the plurality of sacrificial layers; forming alower semiconductor layer on the substrate exposed by the channel hole,the lower semiconductor layer having an upper surface inclined such thata first portion of the upper surface of the lower semiconductor layer islower than a second portion of the upper surface of the lowersemiconductor layer; forming a vertical insulating pattern on an innerwall of the channel hole; and forming a vertical channel pattern on aninner surface of the vertical insulating pattern and contacting thelower semiconductor layer in the channel hole, wherein a first level ofa bottom of the vertical channel pattern is lower than a second level ofthe first portion of the upper surface of the lower semiconductor layer.11. The method for manufacturing a semiconductor memory device of claim10, wherein the forming of the vertical insulating pattern includes:forming a vertical insulating layer on the inner wall of the channelhole and on a top of the lower semiconductor layer; and anisotropicallyetching the vertical insulating layer on the top of the lowersemiconductor layer such that the lower semiconductor layer includes arecess region recessed concavely toward the substrate, and wherein thefirst portion of the upper surface of the lower semiconductor layer isclosest to the substrate.
 12. The method for manufacturing asemiconductor memory device of claim 11, further comprising: forming asacrificial channel layer in the channel hole; anisotropically etchingthe sacrificial channel layer with the vertical insulating layer; andremoving the sacrificial channel layer.
 13. The method for manufacturinga semiconductor memory device of claim 12, further comprising partiallyetching the lower semiconductor layer that overlaps with the sacrificialchannel layer.
 14. The method for manufacturing a semiconductor memorydevice of claim 11, wherein an outer surface of a lower part of thevertical channel pattern contacts the lower semiconductor layer along acurve of the recess region.
 15. The method for manufacturing asemiconductor memory device of claim 10, wherein the vertical insulatingpattern comprises: a tunnel insulating layer contacting a surface of thevertical channel pattern; a charge storing layer positioned between thetunnel insulating layer and the stacking structure; and a blockinginsulating layer positioned between the charge storing layer and thestacking structure, and wherein each of the tunnel insulating layer, thecharge storing layer, and the blocking insulating layer comprises avertical part that extends in a vertical direction to the substrate, andwherein each of the blocking insulating layer and the charge storinglayer comprises a protrusion that is connected with the vertical partthereof and extends on the lower semiconductor layer.
 16. The method formanufacturing a semiconductor memory device of claim 10, wherein afterthe forming of the vertical insulating pattern, a lower part of thechannel hole has a first width above a lowest contact point in which thechannel hole contacts the vertical insulating pattern, and a secondwidth below the lowest contact point, and wherein the first width isequal to or greater than the second width.
 17. The method formanufacturing a semiconductor memory device of claim 10, furthercomprising forming a first region doped with a first impurity within thelower semiconductor layer through an ion injection process after theforming of the lower semiconductor layer.
 18. The method formanufacturing a semiconductor memory device of claim 10, wherein anupper part of the vertical channel pattern contacting the verticalinsulating pattern has a first thickness, wherein a lower part of thevertical channel pattern contacting the lower semiconductor layer has asecond thickness, and wherein the second thickness is substantiallyequal to the first thickness.
 19. A method for manufacturing asemiconductor memory device, comprising: forming a stacking structure byalternately stacking a plurality of insulating layers and a plurality ofsacrificial layers on a substrate; forming a channel hole by penetratingthe plurality of insulating layers and the plurality of sacrificiallayers; forming a lower semiconductor layer on the substrate exposed bythe channel hole; forming a vertical insulating pattern on an inner wallof the channel hole; and forming a vertical channel pattern on an innersurface of the vertical insulating pattern and contacting the lowersemiconductor layer in the channel hole, wherein an upper surface of thelower semiconductor layer is inclined such that a first portion of theupper surface of the lower semiconductor layer is lower than a secondportion of the upper surface of the lower semiconductor layer, and afirst level of an upper surface of a lower part of the vertical channelpattern contacting the lower semiconductor layer is lower than a secondlevel of the second portion of the upper surface of the lowersemiconductor layer.
 20. The method of claim 19, wherein the firstportion of the upper surface of the lower semiconductor layer is closestto the substrate.
 21. The method of claim 20, wherein a third level of abottom of the vertical channel pattern is lower than a fourth level ofthe first portion of the upper surface of the lower semiconductor layer.22. The method for manufacturing a semiconductor memory device of claim20, wherein after the forming of the vertical insulating pattern, alower part of the channel hole has a first width above a lowest contactpoint in which the channel hole contacts the vertical insulatingpattern, and a second width below the lowest contact point, and whereinthe first width is equal to or greater than the second width.
 23. Amethod for manufacturing a semiconductor memory device, comprising:forming a stacking structure by alternately stacking a plurality ofinsulating layers and a plurality of sacrificial layers on a substrate;forming a channel hole by penetrating the plurality of insulating layersand the plurality of sacrificial layers; forming a lower semiconductorlayer on the substrate exposed by the channel hole; forming a firstregion doped with a first impurity within the lower semiconductor layerthrough an ion injection process; forming a vertical insulating patternon an inner wall of the channel hole; and forming a vertical channelpattern on an inner surface of the vertical insulating pattern andcontacting the lower semiconductor layer in the channel hole.
 24. Themethod for manufacturing a semiconductor device of claim 23, furthercomprising forming a second region doped with a second impurity,different from the first impurity, within the lower semiconductor layer.25. The method for manufacturing a semiconductor device of claim 24,wherein the first region comprises a largest content of the firstimpurity among a plurality of regions of the lower semiconductor layerthat are doped with the first impurity, and the second region comprisesa largest content of the second impurity among a plurality of regions ofthe lower semiconductor layer that are doped with the second impurity,and a first width of the first region is different from a second widthof the second region.
 26. The method for manufacturing a semiconductordevice of claim 23, wherein an upper surface of the lower semiconductorlayer is inclined such that a first portion of the upper surface of thelower semiconductor layer is lower than a second portion of the uppersurface of the lower semiconductor layer, and a first level of an uppersurface of a lower part of the vertical channel pattern contacting thelower semiconductor layer is lower than a second level of the firstportion of the upper surface of the lower semiconductor layer.
 27. Themethod for manufacturing a semiconductor device of claim 23, wherein theforming of the first region is performed after the forming of the lowersemiconductor layer.
 28. The method for manufacturing a semiconductordevice of claim 23, wherein the forming of the first region is performedbefore the forming of the vertical channel pattern.
 29. The method formanufacturing a semiconductor device of claim 23, wherein the lowersemiconductor layer has an upper surface inclined such that a firstportion of the upper surface of the lower semiconductor layer is lowerthan a second portion of the upper surface of the lower semiconductorlayer, and a first level of a bottom of the vertical channel pattern islower than a second level of the first portion of the upper surface ofthe lower semiconductor layer.